Power devices are widely used to carry large currents at high voltages. Since the early 1950's, developers of electronic power systems began to base their high power systems on semiconductor devices.
The power bipolar transistor was first developed in the early 1950's, and its technology has matured to a high degree, allowing the fabrication of devices with current handling capabilities of several hundred amperes and blocking voltages of 600 volts. However, despite the attractive power ratings achieved for bipolar transistors, there are several fundamental drawbacks in their operating characteristics. First, the bipolar transistor is a current-controlled device. A large base-drive current, typically one fifth to one tenth of the collector current, is required to maintain the power bipolar transistor in the on state. Even larger reverse base drive currents are necessary to obtain high speed turn-off. These characteristics make the base drive circuitry complex and expensive.
Bipolar transistors are also vulnerable to a second breakdown failure mode under the simultaneous application of a high current and high voltage to the device, as would commonly be required in inductive power circuits. It is also difficult to parallel bipolar power devices because the forward voltage drop in bipolar transistors decreases with increasing temperature. This decrease in forward voltage drop promotes diversion of the current to a single device which can lead to device failure.
The power Field Effect Transistor (FET) was developed to solve the performance limitations of power bipolar transistors. Power FETs are typically variants of the Insulated Gate FET (IGFET) or the Metal Insulator Semiconductor FET (MISFET). These device types are commonly referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFET) because they include a conducting gate electrode, typically metal, that is separated from a semiconductor surface by an intervening insulator, typically silicon dioxide. Accordingly, all field effect transistors which use a conducting gate electrode separated from a semiconductor surface by an intervening insulator will be referred to herein as MOSFETs.
The power MOSFET applies a control signal to the metal gate electrode that is separated from the semiconductor surface by an oxide. Accordingly, the control signal required is essentially a bias voltage, with no significant steady-state gate current flow in either the on-state or the off-state. Even when switching between these states, the gate current is small because it only serves to charge and discharge the input gate capacitance. The high input impedance is a primary feature of the power MOSFET that greatly simplifies the gate drive circuitry and reduces the cost of the power electronics.
Moreover, because current conduction in the MOSFET occurs through majority carrier transport only, no delays are observed as a result of storage or recombination of minority carriers in power MOSFETs during turn on. Their switching speed is therefore orders of magnitude faster than that of bipolar transistors. Power MOSFETs also possess an excellent safe operating area. That is, they can withstand the simultaneous application of high current and voltage for a short duration without undergoing destructive failure due to second breakdown. Power MOSFETs can also easily be paralleled, because the forward voltage drop of power MOSFETs increases with increasing temperature. This feature promotes an even current distribution in parallel devices.
In many present day power devices, large numbers of parallel-connected individual bipolar, MOS or other devices, commonly referred to as "cells", are fabricated in parallel in a single semiconductor integrated circuit, using well known microelectronic manufacturing techniques. Presently, up to 100,000 or more individual low current MOS-gated cells may be fabricated in parallel to produce a power device. The cells may be grouped in "cell blocks" each containing at least one cell and typically containing up to 1000 or more cells which are electrically connected in parallel. A power device may include up to 100 or more cell blocks, which are electrically connected in parallel between common source, drain and gate electrodes.
A major concern in fabricating a high current power device containing a large number of parallel cells is the yield of the resulting chip. In particular, it is difficult to provide a high yield high current power device in view of the defect rate of the individual cells on the semiconductor substrate. Since these individual cells are electrically connected in parallel, a short circuit in one cell renders the power device unusable. Accordingly, in practice, yields of only 30% are typically obtained even for relatively small chips with size of 0.25 inch by 0.25 inch.
One attempt at overcoming this yield problem is described in the article "A Large Area MOS-GTO with Wafer-repair Technique" by Stoisiek, et al., IEDM, 1987, pages 666-669. In this approach a MOS power device is fabricated out of about 300,000 individual MOS cells on a semiconductor substrate. The individual MOS cells are grouped into cell blocks, and each cell block is individually tested for faulty operation. The substrate is covered with an insulating layer, and a via hole pattern is etched into the insulating layer according to the results of the previous operational measurements, i.e. holes are etched only over the cell blocks without a fault. Consequently, the faulty cell blocks are insulated from the rest of the device. A metal layer connects all the operational cell blocks through the via holes. Thus, shorted cells are prevented from causing other cells to short circuit because they are not connected in parallel with the functional cells.
While the above described technique prevents a short circuit in one or more individual cell blocks from destroying the entire power device, this technique is not amenable to mass production of power devices. A custom mask must be designed for every wafer so that a via hole pattern may be etched on the insulating layer to connect only the fault-free cells or cell blocks. The cost of individual masks and the turn around time for designing the masks and then forming the individually designed via patterns makes the resultant devices prohibitively expensive. In addition, these operations increase the number of processing steps and add to overall fabrication cost for the large area device.
Another technique for overcoming the yield problem is described in U.S. Pat. No. 5,021,861 by the present inventor entitled Integrated Circuit Power Device with Automatic Removal of Defective Devices and Method of Fabricating Same. As described in the patent, defective cells are automatically disabled upon application of power to the power device without the need for testing of individual cells or customized mask generation. A fusible link formed of a low melting point conductor connects each cell block to the common electrode of the power device. For example, in a MOS-gated device, a fusible link connects the gate electrode of the power device to the common gate of each cell block. The fusible link is designed to melt in response to a defect related short circuit current in the associated cell block. Accordingly, when the device is initially powered, all fusible links associated with short circuited individual cells will melt, so that the cell block containing the defective cell is disconnected. See also U.S. Pat. Nos. 4,742,425 entitled Multiple-Cell Transistor with Base and Emitter Fuse Links, and 4,942,308 entitled Power Transistor Monolithic Integrated Structure, both to Conzelmann et al.
The above described technique eliminates the need to design and fabricate custom masks. Unfortunately, the minimum fusing current required to melt a fusible link is about ten milliamperes, and leakage currents below this value will not melt the fusible link. Conventional power devices possess gate leakage currents in the range of microamperes, about one thousand times less than the required fusing current. Accordingly, power devices including the automatic disabling fusible links have gate leakage currents which can be one thousand times the acceptable level.
Still another technique for overcoming the yield problem is described in the pending U.S. patent application, Ser. No. 07/895339, by the present inventor entitled Integrated Circuit Power Device With External Disabling of Defective Devices And Method Of Fabricating Same. As described in this patent application, defective cells are disabled during the testing process without the need for a customized mask. A fusible link connects each cell block to a common electrode of the power device. Furthermore, external measurement access means are formed in the integrated circuit allowing access to the fusible link from both the cell block and common electrode ends. For example, in a MOS-gated device, a fusible link connects the gate electrode of the power device to the common gate of each cell block, and individual test pads allow access to both ends of each fusible link. An external testing means is used to test each cell block for proper operation. An externally activated disabling means is used to disable nonfunctional cell blocks by disabling the fusible link with a high current.
The above described technique eliminates the need to design and fabricate custom masks, and there are no added fabrication steps. This technique allows the use of low resistance fuses for high speed operation. This technique also allows the external disabling means to disable cell blocks which have a leakage current above any specified level. However, the external testing of each cell block is a time consuming and costly process. Thus, the technique presents a tradeoff between leakage current and manufacturing time and cost. In view of the above, there is a need for an integrated circuit power device which maintains a low leakage current and allows high speed operation while eliminating the need to test each cell block individually.